An integrated circuit is typically formed on a substrate by the sequential deposition of conductive, semiconductive, or insulative layers on a silicon wafer. A variety of fabrication processes require planarization of a layer on the substrate. For certain applications, e.g., polishing of a metal layer to form vias, plugs, and lines in the trenches of a patterned layer, an overlying layer is planarized until the top surface of a patterned layer is exposed. In other applications, e.g., planarization of a dielectric layer for photolithography, an overlying layer is polished until a desired thickness remains over the underlying layer.
Chemical mechanical polishing (CMP) is one accepted method of planarization. This planarization method typically requires that the substrate be mounted on a carrier head. The exposed surface of the substrate is typically placed against a rotating polishing pad. The carrier head provides a controllable load on the substrate to push it against the polishing pad. A polishing liquid, such as slurry with abrasive particles, is typically supplied to the surface of the polishing pad.
One objective of a chemical mechanical polishing process is polishing uniformity. If different areas on the substrate are polished at different rates, then it is possible for some areas of the substrate to have too much material removed (“overpolishing”) or too little material removed (“underpolishing”). In addition to planarization, polishing pads can be used for finishing operations such as buffing.
Polishing pads are typically made by molding, casting or sintering polyurethane materials. In the case of molding, the polishing pads can be made one at a time, e.g., by injection molding. In the case of casting, the liquid precursor is cast and cured into a cake, which is subsequently sliced into individual pad pieces. These pad pieces can then be machined to a final thickness. Grooves can be machined into the polishing surface, or be formed as part of the injection molding process.